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1 of 20 111803 features unique 1-wire ? interface requires only one port pin for communication derives power from data line (parasite power)does not need a local power supply multi-drop capability simplifies distributed temperature sensing applications requires no external components 0.5 c accuracy from C10c to +85c measures temperatures from C55c to +100c (C67f to +212f) 9-bit thermometer resolution converts temperature in 750 ms (max.) userCdefinable non-volatile temperature alarm settings alarm search command identifies and addresses devices whose temperature is outside of programmed limits (temperature alarm condition) ideal for use in remote sensing applications (e.g., temperature probes) that do not have a local power source pin assignment pin description gnd - ground dq - data in/out nc - no connect description the ds18s20-par digital thermometer provides 9Cbit centigrade temperature measurements and has an alarm function with nonvolatile user -programmable upper and lower tr igger points. the ds18s20-par does not need an external power supply because it de rives power directly from the data line (parasite power). the ds18s20-par communi cates over a 1-wire bus, which by definition requires only one data line (and ground) for communication with a central microprocessor. it has an operating temperature range of C55c to +100c and is accurate to 0.5 c over a range of C10c to +85c. each ds18s20-par has a unique 64-bit identification code, which allows multiple ds18s20-pars to function on the same 1Cwire bus; thus, it is simp le to use one microprocessor to control many ds18s20-pars distributed over a larg e area. applications that can benefit from this feature include hvac environmental controls, temperature monito ring systems inside buildings, equipment or machinery, and process monitoring and control systems. ds18s20-par 1-wire parasite-powe r digital thermomete r www.maxim - ic.com to-92 ( ds18s20-par ) 1 ( bottom view ) 23 dallas 18s20p 1 gnd dq nc 23 1-wire is a registered trademark of dallas semiconductor. downloaded from: http:///
ds18s20-par 2 of 20 detailed pin descriptions table 1 pin symbol description 1 gnd ground. 2d q data input/output pin. open-drain 1-wire interface pin. also provides power to the device when used in parasite power mode (see parasite power section.) 3n c no connect. doesnt connect to internal circuit. overview the ds18s20-par uses dallas exclusive 1-wire bus protocol that implements bus communication using one control signal. the control line requires a weak pullup resistor since all devices are linked to the bus via a 3-state or open-drain port (the dq pin in the case of the ds18s20-par). in this bus system, the microprocessor (the master device) identifies a nd addresses devices on the bus using each devices unique 64-bit code. because each device has a unique code, the number of devices that can be addressed on one bus is virtually unlimited. the 1-wire bus protocol, including detailed explanations of the commands and time slots, is covered in the 1-wire bus system section of this datasheet. an important feature of the ds18s20-par is its ab ility to operate without an external power supply. power is instead supplied through the 1-wire pullup re sistor via the dq pin when the bus is high. the high bus signal also charges an internal capacitor (c pp ), which then supplies power to the device when the bus is low. this method of deriving power from the 1-wire bus is referred to as parasite power. figure 1 shows a block diagram of the ds18s20-par, and pin descriptions are given in table 1. the 64-bit rom stores the devices unique serial code . the scratchpad memory contains the 2-byte temperature register that stores the digital output fro m the temperature sensor. in addition, the scratchpad provides access to the 1-byte upper and lower alarm trigger registers (t h and t l ). the t h and t l registers are nonvolatile (eeprom), so they will retain their data when the device is powered down. ds18s20-par block diagram figure 1 c pp v pu 4.7k 64-bit rom and 1-wire port d q internal v dd parasite power circuit memory control logic scratchpad 8-bit crc generator temperature sensor alarm high trigger (t h ) register (eeprom) alarm low trigger (t l ) register (eeprom) gnd ds18s20-par downloaded from: http:///
ds18s20-par 3 of 20 parasite power the ds18s20-pars parasite power ci rcuit allows the ds18s20-par to operate without a local external power supply. this ability is especially useful for a pplications that require re mote temperature sensing or that are very space constrained. figure 1 shows the ds18s20-pars parasite- power control circuitry, which steals power from the 1-wire bus via the dq pin when the bus is high. the stolen charge powers the ds18s20-par while the bus is high, and some of the charge is stored on the parasite power capacitor (c pp ) to provide power when the bus is low. the 1-wire bus and c pp can provide sufficient parasite power to the ds18s20-par for most operations as long as the specified timing and voltage requirements are met (refer to the dc electrical characteristics and the ac electrical characteristics sections of this data sheet). however, when the ds18s20-par is performing temp erature conversions or copying data from the scratchpad memory to eeprom, the operating current can be as high as 1.5 ma. this current can cause an unacceptable voltage drop across the weak 1-wire pullup resistor and is more current than can be supplied by c pp . to assure that the ds18s20-par has su fficient supply current, it is necessary to provide a strong pullup on the 1-wire bus whenever te mperature conversions are taking place or data is being copied from the scratchpad to eeprom. this can be accomplished by using a mosfet to pull the bus directly to the rail as shown in figure 2. the 1-wire bus must be switched to the strong pullup within 10 s (max) after a convert t [44h] or copy sc ratchpad [48h] command is issued, and the bus must be held high by the pullup for the duration of the conversion (t conv ) or data transfer (t wr = 10 ms). no other activity can take place on the 1-wire bus while the pullup is enabled. supplying the ds18s20-par during temperature conversions figure 2 operation C measuring temperature the core functionality of the ds18s20-par is its dir ect-to-digital temperature sensor. the temperature sensor output has 9-bit reso lution, which corresponds to 0.5 c steps. the ds18s20-par powers-up in a low-power idle state; to initiate a temperature meas urement and a-to-d conversion, the master must issue a convert t [44h] command. following the conversion, th e resulting thermal data is stored in the 2-byte temperature register in the scratchpad memory and the ds18s20-par returns to its idle state. the ds18s20-par output data is calibrated in degrees centigrade; for fahrenheit applications, a lookup table or conversion routine must be use d. the temperature data is stored as a 16-bit sign-extended twos complement number in the temperature register (see figure 3). the sign bits (s) indicate if the temperature is positive or negative: for positive numbe rs s = 0 and for negative numbers s = 1. table 2 gives examples of digital output data and the corresponding temperature reading. resolutions greater than 9 bits can be calculated using the data from the temperature, count remain and count per c registers in the scratchpad. note that the count per c register is hard-wired to v pu v pu 4.7k 1-wire bus micro- processor ds18s20-pa r gnd dq to other 1-wire devices downloaded from: http:///
ds18s20-par 4 of 20 16 (10h). after reading the scratchpad, the temp_ read value is obtained by truncating the 0.5 c bit (bit 0) from the temperature data (see figure 3). the extended resolution temperature can then be calculated using the following equation: c per count remain count c per count read temp e temperatur _ _ _ _ _ 25.0 _ temperature register format figure 3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ls byte 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ms byte ssssssss temperature/data relationship table 2 temperature digital output (binary) digital output (hex) +85.0c* 0000 0000 1010 1010 00aah +25.0c 0000 0000 0011 0010 0032h +0.5c 0000 0000 0000 0001 0001h 0c 0000 0000 0000 0000 0000h -0.5c 1111 1111 1111 1111 ffffh -25.0c 1111 1111 1100 1110 ffceh -55.0c 1111 1111 1001 0010 ff92h *the power-on reset value of the temperature register is +85c operation C alarm signaling after the ds18s20-par performs a te mperature conversion, the temperature value is compared to the user-defined twos complement alarm trigger values stored in the 1-byte t h and t l registers (see figure 4). the sign bit (s) indicates if the value is positive or negative: for positive numbers s = 0 and for negative numbers s = 1. the t h and t l registers are nonvolatile (eepro m) so they will retain data when the device is powered down. t h and t l can be accessed through bytes 2 and 3 of the scratchpad as explained in the memory section of this datasheet. t h and t l register format figure 4 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 s2 6 2 5 2 5 2 5 2 2 2 1 2 0 only bits 8 through 1 of the temperature register are used in the t h and t l comparison since t h and t l are 8-bit registers. if the result of a temperature measurement is higher than t h or lower than t l , an alarm condition exists and an alarm flag is set inside the ds18s20-par. this flag is updated after every temperature measurement; therefore, if the alarm condition goes away, the flag will be turned off after the next temperature conversion. the master device can check the alarm flag status of all ds ds18s20-pars on the bus by issuing an alarm search [ech] command. any ds18s20-pars w ith a set alarm flag will respond to the command, downloaded from: http:///
ds18s20-par 5 of 20 so the master can determine exact ly which ds18s20-pars have experi enced an alarm condition. if an alarm condition exists and the t h or t l settings have changed, another temperature conversion should be done to validate the alarm condition. 64-bit lasered rom code each ds18s20-par contains a unique 64Cb it code (see figure 5) stored in rom. the least significant 8 bits of the rom code contain the ds18s20-pars 1Cwire family code : 10h. the next 48 bits contain a unique serial number. the most significant 8 bits contain a cyclic redundancy check (crc) byte that is calculated from the first 56 bits of the rom code. a detailed explanation of the crc bits is provided in the crc generation section. the 64Cbit rom code and associated rom function control logic allow the ds18s20-par to operate as a 1Cwire device using the protocol detailed in the 1-wire bus system section of this datasheet. 64-bit lasered rom code figure 5 8-bit crc 48-bit serial number 8-bit family code (10h) memory the ds18s20-pars memory is organized as shown in figure 6. the memory consists of an sram scratchpad with nonvola tile eeprom storage for the high and low alarm trigger registers (t h and t l ). note that if the ds18s20-par al arm function is not used, the t h and t l registers can serve as general- purpose memory. all memory commands are described in detail in the ds18s20-par function commands section. byte 0 and byte 1 of the scratchpad contain the lsb and the msb of the temperature register, respectively. these bytes are read-onl y. bytes 2 and 3 provide access to t h and t l registers. bytes 4 and 5 are reserved for internal use by the device a nd cannot be overwritten; thes e bytes will return all 1s when read. bytes 6 and 7 contain the count remain and count per oc registers, which can be used to calculate extended resolution results as explained in the operation C measuring temperature section. byte 8 of the scratchpad is read-only and contains the cyclic redundancy check (crc) code for bytes 0 through 7 of the scratchpad. the ds18s20-par generates this crc using the method described in the crc generation section. data is written to bytes 2 and 3 of the scratchpad using the write scratchpad [4eh] command; the data must be transmitted to the ds18s20-par starting with the least significant bit of byte 2. to verify data integrity, the scratchpad can be read (using the read scratchpad [beh] command) after the data is written. when reading the scratchpad, data is transferred over the 1-wire bus starting with the least significant bit of byte 0. to transfer the t h and t l data from the scratchpad to eeprom, the master must issue the copy scratchpad [48h] command. data in the eeprom registers is retained when th e device is powered down; at power-up the eeprom data is reloaded into the corresponding scratchpad lo cations. data can also be reloaded from eeprom to the scratchpad at any time using the recall e 2 [b8h] command. the master can issue read time slots (see the 1-wire bus system section) following the recall e 2 command and the ds18s20-par will indicate the status of the recall by transmitting 0 while the recall is in progress and 1 when the recall is done. msb msb lsb lsb lsb msb downloaded from: http:///
ds18s20-par 6 of 20 ds18s20-par memory map figure 6 scratchpad (power-up state) byte 0 temperature lsb (aah) byte 1 temperature msb (00h) eeprom byte 2 t h register or user byte 1* t h register or user byte 1 byte 3 t l register or user byte 2* t l register or user byte 2 byte 4 reserved (ffh) byte 5 reserved (ffh) byte 6 count remain (0ch) byte 7 count per c (10h) byte 8 crc* * power-up state depends on value(s) stored in eeprom crc generation crc bytes are provided as part of the ds18s20-pars 64-bit rom code and in the 9 th byte of the scratchpad memory. the rom code crc is calculated from the first 56 bits of the rom code and is contained in the most significant byte of the rom. the scratchpad crc is calculated from the data stored in the scratchpad, and therefore it changes when the data in the scratchpad changes. the crcs provide the bus master with a met hod of data validation when data is read from the ds18s20-par. to verify that data has been read correctly, the bus master must re-calculate the crc from the received data and then compare this value to either the rom code crc (for rom reads) or to the scratchpad crc (for scratchpad reads). if the calculate d crc matches the read crc, the data has been received error free. the comparison of crc values and the decision to continue with an operation are determined entirely by the bus master. there is no circuitry inside the ds18s20-par that prevents a command sequence from proceeding if the ds18s20-par crc (r om or scratchpad) does not ma tch the value generated by the bus master. the equivalent polynomial function of the crc (rom or scratchpad) is: crc = x 8 + x 5 + x 4 + 1 the bus master can re-calculate the crc and compare it to the crc values from the ds18s20-par using the polynomial generator shown in figure 7. this circuit consists of a shift register and xor gates, and the shift register bits are initialized to 0. starting with the least significant bit of the rom code or the least significant bit of byte 0 in the scratchpad, one bit at a time should shifted into the shift register. after shifting in the 56 th bit from the rom or the most significant bit of byte 7 from the scratchpad, the polynomial generator will contain the re-calculated crc. next, the 8-bit rom code or scratchpad crc from the ds18s20-par must be shifted into the circuit. at this point, if the re-calculated crc was correct, the shift register will contain all 0s. a dditional information about the dallas 1-wire cyclic redundancy check is available in application no te 27 entitled understa nding and using cyclic redundancy checks with dallas semiconductor touc h memory products. crc generator figure 7 (msb) (lsb) xor xor xor input (85c) downloaded from: http:///
ds18s20-par 7 of 20 1-wire bus system the 1-wire bus system uses a single bus master to control one or more slave devices. the ds18s20- par is always a slave. when there is only one slave on the bus, the system is referred to as a single- drop system; the system is multi-drop if there are multiple slaves on the bus. all data and commands are transmitted least significant bit first over the 1-wire bus. the following discussion of the 1-wire bus syst em is broken down into three topics: hardware configuration, transaction se quence, and 1-wire signaling (signal types and timing). hardware configuration the 1-wire bus has by definition only a single data line. each device (master or slave) interfaces to the data line via an open drain or 3Cstate port. this allows each device to release the data line when the device is not transmitting data so the bus is available for use by another device. the 1-wire port of the ds18s20-par (the dq pin) is open drai n with an internal circuit equiva lent to that shown in figure 8. the 1-wire bus requires an external pullup resistor of approximately 5 k ; thus, the idle state for the 1- wire bus is high. if for any reason a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. infinite recovery time can occur between bits so long as the 1-wire bus is in the inactive (high) state during the recovery period. if the bus is held low for more than 480 s, all components on the bus will be re set. in addition, to assure th at the ds18s20-par has sufficient supply current during temperature conversions, it is necessary to provide a strong pullup (such as a mosfet) on the 1-wire bus whenever temperature conversions or eeprom writes are taking place (as described in the para site power section). hardware configuration figure 8 transaction sequence the transaction sequence for accessi ng the ds18s20-par is as follows: step 1. initialization step 2. rom command (followed by any required data exchange) step 3. ds18s20-par function command (follo wed by any required data exchange) 5 a typ. ds18s20-par 1-wire port 100 m os fet t x r x dqpin v pu 4.7k r x t x r x = receive t x = transmit 1-wire bus v pu micro- processor strong pullup downloaded from: http:///
ds18s20-par 8 of 20 it is very important to follow the transaction se quence every time the ds18s20-par is accessed, as the ds18s20-par will not respond if any steps in the sequ ence are missing or out of order. exceptions to this rule are the search rom [f0h] and alarm search [ech] commands. after issuing either of these rom commands, the master must return to step 1 in the sequence. initialization all transactions on the 1-wire bus begin with an initialization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that slave devices (suc h as the ds18s20-par) are on the bus and are ready to operate. timing for the reset and presence pulses is detailed in the 1-wire signaling section. rom commands after the bus master has detected a presen ce pulse, it can issue a rom command. these commands operate on the unique 64Cbit rom codes of each slave device and allow the master to single out a specific device if many are present on the 1-wire bus. these commands also allow the master to determine how many and what types of devices are present on the bus or if any device has experienced an alarm condition. there are five rom commands, and ea ch command is 8 bits long. the master device must issue an appropriate rom command before issuing a ds18s20-par function command. a flowchart for operation of the rom commands is shown in figure 9. search rom [f0h] when a system is initially powered up, the master mu st identify the rom codes of all slave devices on the bus, which allows the master to determine the number of slaves and their device types. the master learns the rom codes through a process of elimination that requires the master to perform a search rom cycle (i.e., search rom command followed by data exch ange) as many times as necessary to identify all of the slave devices. if there is only one slave on the bus, the simpler read rom command (see below) can be used in place of the search rom process. for a detailed explanation of the search rom procedure, refer to the ibutton ? book of standards at www.i button.com/ibuttons/standard.pdf . after every search rom cycle, the bus master must return to step 1 (initialization) in the transaction sequence. read rom [33h] this command can only be used when there is one slave on the bus. it allows the bus master to read the slaves 64-bit rom code without using the search rom procedure. if this command is used when there is more than one slave present on the bus, a data collision will occur when all the slaves attempt to respond at the same time. match rom [55h] the match rom command followed by a 64Cbit rom code sequence allows the bus master to address a specific slave device on a multi-drop or single-drop bus . only the slave that exactly matches the 64Cbit rom code sequence will respond to th e function command issued by the master; all other slaves on the bus will wait for a reset pulse. skip rom [cch] the master can use this command to address all de vices on the bus simultaneously without sending out any rom code information. for example, the mast er can make all ds18s20-pars on the bus perform simultaneous temperature conversions by issuing a skip rom command followed by a convert t [44h] command. note, however, that the skip rom comma nd can only be followed by the read scratchpad [beh] command when there is one slave on the bus. this sequence saves time by allowing the master to ibutton is a registered trademark of dallas semiconductor. downloaded from: http:///
ds18s20-par 9 of 20 read from the device without sending its 64Cbit rom code. this sequence will cause a data collision on the bus if there is more than one slave since multiple devices will attempt to transmit data simultaneously. alarm search [ech] the operation of this command is identical to the operation of the search rom command except that only slaves with a set alarm flag will respond. this command allows the master device to determine if any ds18s20-pars experienced an alarm condition during the most recent temperature conversion. after every alarm search cycle (i.e., alarm search command followed by data exchange), the bus master must return to step 1 (initialization) in the tran saction sequence. refer to the operation C alarm signaling section for an explanation of alarm flag operation. ds18s20-par function commands after the bus master has used a rom command to address the ds18s20-par with which it wishes to communicate, the master can issue one of th e ds18s20-par function commands. these commands allow the master to write to and read from the ds18s20-pars scratchpad memory, initiate temperature conversions and determine the power supply mode . the ds18s20-par function commands, which are described below, are summarized in table 4 and illustrated by the flowchart in figure 10. convert t [44h] this command initiates a single temp erature conversion. following th e conversion, the resulting thermal data is stored in the temperature register, count remain register and count per c register in th e scratchpad memory, and the ds18s20-par returns to its low-power idle state. within 10 s (max) after this command is issued the master must enable a strong pullup on the 1-wire bus for the duration of the conversion (t conv ) as described in the parasite power section. write scratchpad [4eh] this command allows the master to write 2 bytes of data to the ds18s20-pars scratchpad. the first byte is written into the t h register (byte 2 of the scratchpad), and the second byte is written into the t l register (byte 3 of the scratchpad). data must be transmitted least significant bit first. bo th bytes must be written before the master issues a reset, or the data may be corrupted. read scratchpad [beh] this command allows the master to read the contents of the scratchpad. the data transfer starts with the least significant bit of byte 0 and continues through the scratchpad until the 9 th byte (byte 8 C crc) is read. if only part of the scratchpa d contents is required, the master may issue a reset to terminate reading at any time. copy scratchpad [48h] this command copies the cont ents of the scratchpad t h and t l registers (bytes 2 and 3) to eeprom. within 10 s (max) after this command is issued the master must enable a strong pullup on the 1-wire bus for at least 10 ms as described in the parasite power section. recall e 2 [b8h] this command recalls the alarm trigger values (t h and t l ) from eeprom and places the data in bytes 2 and 3, respectively, in the scratchpad memory. the master device can issue read time slots (see the 1- wire bus system section) following the recall e 2 command and the ds18s20-par will indicate the status of the recall by transmitting 0 while the recall is in progress and 1 when the recall is done. the recall operation happens automatically at power-up, so va lid data is available in the scratchpad as soon as power is applied to the device. downloaded from: http:///
ds18s20-par 10 of 20 ds18s20-par function command set table 4 command description protocol 1-wire bus activity after command is issued notes temperature conversion commands convert t initiates temperature conversion. 44h none 1 memory commands read scratchpad reads the entire scratchpad including the crc byte. beh ds18s20-par transmits up to 9 data bytes to master. 2 write scratchpad writes data into scratchpad bytes 2 and 3 (t h and t l ). 4eh master transmits 2 data bytes to ds18s20-par. 3 copy scratchpad copies t h and t l data from the scratchpad to eeprom. 48h none 1 recall e 2 recalls t h and t l data from eeprom to the scratchpad. b8h ds18s20-par transmits recall status to master. notes:1. the master must enable a strong pullup on the 1- wire bus during temperature conversions and copies from the scratchpad to eeprom. no other bus activity may take place during this time. 2. the master can interrupt the transmission of data at any time by issuing a reset. 3. both bytes must be written before a reset is issued. downloaded from: http:///
ds18s20-par 11 of 20 rom commands flow chart figure 9 cch skip rom command master t x reset pulse ds18s20-par t x presence pulse master t x rom command 33h read rom command 55h match rom command f0h search rom command ech alarm search command master t x bit 0 bit 0 mat c h? master t x bit 1 bit 1 mat c h? bit 63 match? master t x bit 63 n y yyy y nn n n n n n y y y bit 0 mat c h? bit 1 mat c h? bit 63 match? n n n y y y ds18s20-par t x family code 1 byte ds18s20-par t x serial number 6 bytes ds18s20-par t x crc byte ds18s20-par t x bit 0 ds18s20-par t x bit 0 master t x bit 0 n y device(s) with alarm flag set? initialization sequence master t x function command (figure 10) ds18s20-par t x bit 0 ds18s20-par t x bit 0 master t x bit 0 ds18s20-par t x bit 1 ds18s20-par t x bit 1 master t x bit 1 ds18s20-par t x bit 63 ds18s20-par t x bit 63 master t x bit 63 downloaded from: http:///
ds18s20-par 12 of 20 ds18s20-par function commands flow chart figure 10 master t x function command y n 44h convert temperature ? master enables strong pullup on dq ds18s20-par converts temperature master disables strong pullup y n 48h copy scratchpad ? master enables strong pull-up on dq data copied from scratchpad to eeprom master disables strong pullup return to initialization sequence (figure 9) for next transaction y n y beh read scratchpad ? have 8 bytes been read ? n master t x reset ? master r x data byte from scratchpad n y master r x scratchpad crc byte master r x 1s y n b8h recall e 2 ? master begins data recall from e 2 prom device busy recalling data ? n y master r x 0s master t x t h byte to scratchpad y n 4eh write scratchpad ? master t x t l byte to scratchpad downloaded from: http:///
ds18s20-par 13 of 20 1-wire signaling the ds18s20-par uses a strict 1-wire communication protocol to insure data integrity. several signal types are defined by this protoco l: reset pulse, presence pulse, write 0, write 1, read 0, and read 1. all of these signals, with the exception of the presence pulse, are initiated by the bus master. initialization procedure: reset and presence pulses all communication with the ds18s20-par begins with an initialization sequence that consists of a reset pulse from the master followed by a presence pulse from the ds18s20-par. this is illustrated in figure 11. when the ds18s20-par sends the presence pulse in response to the reset, it is indicating to the master that it is on the bus and ready to operate. during the initialization sequence the bus master transmits (t x ) the reset pulse by pulling the 1-wire bus low for a minimum of 480 s. the bus master then releases the bus and goes into receive mode (r x ). when the bus is released, the 5k pullup resistor pulls the 1-wire bus high. when the ds18s20-par detects this rising edge, it waits 15C60 s and then transmits a presence pulse by pulling the 1-wire bus low for 60C240 s. initialization timing figure 11 read/write time slots the bus master writes data to the ds18s20-par during write time slots and reads data from the ds18s20-par during read time slots. one bit of data is transmitted over the 1-wire bus per time slot. write time slots there are two types of write time slots: write 1 time slots and write 0 time slots. the bus master uses a write 1 time slot to write a logic 1 to the ds18s20-par and a write 0 time slot to write a logic 0 to the ds18s20-par. all write time slots must be a minimum of 60 s in duration with a minimum of a 1 s recovery time between individual write slots. both types of write time slots are initiated by the master pulling the 1-wire bus low (see figure 12). to generate a write 1 time slot, after pulling the 1-wire bus low, the bus master must release the 1-wire bus within 15 s. when the bus is released, the 5k pullup resistor will pull the bus high. to generate a write 0 time slot, after pulling the 1-wire bus low, the bus master must continue to hold the bus low for the duration of the time slot (at least 60 s). line type legend bus master pulling low ds18s20-par pulling low resistor p ullu p v pu gnd 1-wire bus 480 s minimum 480 s minimum ds18s20-par t x presence pulse 60-240 s master t x reset pulse master r x ds18s20-pa r waits 15-60 s downloaded from: http:///
ds18s20-par 14 of 20 the ds18s20-par samples the 1-wire bus during a window that lasts from 15 s to 60 s after the master initiates the wr ite time slot. if the bus is high during the sampling window, a 1 is written to the ds18s20-par. if the line is low, a 0 is written to the ds18s20-par. read/write time slot timing diagram figure 12 read time slots the ds18s20-par can only transmit data to the master when the master issues read time slots. therefore, the master must generate read time slots immediately after issuing a read scratchpad [beh] command, so that the ds18s20-par can provide the requested data. in addition, the master can generate read time slots after issuing a recall e 2 [b8h] command to find out the recall status as explained in the ds18s20-par function command section. all read time slots must be a minimum of 60 s in duration with a minimum of a 1 s recovery time between slots. a read time slot is initiated by the master device pulling the 1-wire bus low for a minimum of 1 s and then releasing the bus (see figure 12). after the master initiates the read time slot, the ds18s20-par will begin transmitting a 1 or 0 on bus. the ds18s20-par transmits a 1 by leaving the bus high and transmits a 0 by pulling the bus low. when transmitting a 0, the ds18s20-par will line type legend bus master pulling low ds18s20-par pulling low resistor pullup 45 s 15 s v pu gnd 1-wire bus 60 s < t x 0 < 120 1 s < t rec < ds18s20-par samples min typ ma x 15 s 30 s > 1 s master write 0 slot master write 1 slot ds18s20-par samples min typ ma x v pu gnd 1-wire bus 15 s master read 0 slot master read 1 slot master samples master samples start of slot start of slot > 1 s 1 s < t rec < 15 s 15 s 30 s 15 s > 1 s downloaded from: http:///
ds18s20-par 15 of 20 release the bus by the end of the time slot, and the bus will be pulled back to its high idle state by the pullup resister. output data fro m the ds18s20-par is valid for 15 s after the falling edge that initiated the read time slot. therefore, the master must release the bus and then sample the bus state within 15 s from the start of the slot. figure 13 illustrates that the sum of t init , t rc , and t sample must be less than 15 s for a read time slot. figure 14 shows that system timing margin is maximized by keeping t init and t rc as short as possible and by locating the master sample time during read time slots towards the end of the 15 s period. detailed master read 1 timing figure 13 recommended master read 1 timing figure 14 v pu gnd 1-wire bus 15 s v ih of master t rc t int > 1 s master samples line type legend bus master pulling low resistor pullup v pu gnd 1-wire bus 15 s v ih of master t rc = small t int = small master samples downloaded from: http:///
ds18s20-par 16 of 20 ds18s20-par operation example 1 in this example there is only one ds18s20-pa r on the bus. the master writes to the t h and t l registers in the ds18s20-par scratchpad and then reads the scratchpad and recalculates the crc to verify the data. the master then copies the scratchpad contents to eeprom. master mode data (lsb first) comments tx reset master issues reset pulse. rx presence ds18s20-par responds with presence pulse. tx cch master issues skip rom command. tx 4eh master issues write scratchpad command. tx 2 data bytes master sends two data bytes to scratchpad (t h and t l ). tx reset master issues reset pulse. rx presence ds18s20-par res ponds with presence pulse. tx cch master issues skip rom command. tx beh master issues read scratchpad command. rx 9 data bytes master reads entire scratchpad including crc. the master then recalculates the crc of the first eight data bytes from the scratchpad and compares the calculated crc with the read crc (byte 9). if they match, the master continues; if not, the read operation is repeated. tx reset master issues reset pulse. rx presence ds18s20-par responds with presence pulse. tx cch master issues skip rom command. tx 48h master issues copy scratchpad command. tx dq line held high by strong pullup master applies strong pullup to dq for at least 10 ms while copy operation is in progress. downloaded from: http:///
ds18s20-par 17 of 20 ds18s20-par operation example 2 in this example there are multiple ds18s20-pars on the bus. the bus master initiates a temperature conversion in a specific ds18s20-par and then reads its scratchpad and recalculates the crc to verify the data. master mode data (lsb first) comments tx reset master issues reset pulse. rx presence ds18s20-pars respond with presence pulse. tx 55h master issues match rom command. tx 64-bit rom code master sends ds18s20-par rom code. tx 44h master issues convert t command. tx dq line held high by strong pullup master applies strong pullup to dq for the duration of the conversion (t conv ). tx reset master issues reset pulse. rx presence ds18s20-pars respond with presence pulse. tx 55h master issues match rom command. tx 64-bit rom code master sends ds18s20-par rom code. tx beh master issues read scratchpad command. rx 9 data bytes master reads entire scratchpad including crc. the master then recalculates the crc of the first eight data bytes from the scratchpad and compares the calculated crc with the read crc (byte 9). if they match, the master continues; if not, the read operation is repeated. ds18s20-par operation example 3 in this example there is only one ds18s20-par on the bus. the bus master initiates a temperature conversion then reads the ds18s20- par scratchpad and calculates a hi gher resolution result using the data from the temperature, count remain and count per c registers. master mode data (lsb first) comments tx reset master issues reset pulse. tr presence ds18s20-par responds with presence pulse. tx cch master issues skip rom command. tx 44h master issues convert t command. tx dq line held high by strong pullup master applies strong pullup to dq for the duration of the conversion (t conv ). tx reset master issues reset pulse. rx presence ds18s20-par responds with presence pulse. tx cch master issues skip rom command. tx beh master issues read scratchpad command. rx 9 data bytes master reads entire scratchpad including crc. the master then recalculates the crc of the first eight data bytes from the scratchpad and compares the calculated crc with the read crc (byte 9). if they match, the master continues; if not, the read operation is repeated. the master also calculates the temp_read value and stores the contents of the count remain and count per c registers. tx reset master issues reset pulse. rx presence ds18s20-par responds with presence pulse. - - cpu calculates extended resolution temperature using the equation in the operation - measuring temperature section of this datasheet. downloaded from: http:///
ds18s20-par 18 of 20 absolute maximum ratings* voltage on any pin relative to ground C0.5v to +6.0v operating temperature C55 c to +100 c storage temperature C55 c to +125 c soldering temperature see j-std-020a specification *these are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the opera tion sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (-55c to +100c; v pu =3.0v to 5.5v) parameter symbol condition min typ max units notes pullup supply voltage v pu 3.0 5.5 v 1,2 thermometer error t err -10c to +85c ? c 3 -55c to +100c 2 input logic low v il -0.3 +0.8 v 1,4,5 input logic high v ih 3.0 5.5 v 1,6 sink current i l v i/o =0.4v 4.0 ma 1 active current i dqa 1 1.5 ma 7 dq input current i dq 5 a 8 drift 0.2 c 9 notes:1. all voltages are referenced to ground. 2. the pullup supply voltage specification assumes that the pullup device (resistor or transistor) is ideal, and therefore the high level of the pullup is equal to v pu . in order to meet the v ih spec of the ds18s20-par, the actual supply rail for the strong pu llup transistor must include margin for the voltage drop across the transistor when it is turned on; thus: v pu_actual = v pu_ideal + v transistor . 3. see typical performance curve in figure 15. 4. logic low voltages are specified at a sink current of 4 ma. 5. to always guarantee a presence pulse unde r low voltage parasite power conditions, v ilmax may have to be reduced to as low as 0.5v. 6. logic high voltages are specified at a source current of 1 ma. 7. active current refers to supply current during active temperature convers ions or eeprom writes. 8. dq line is high (hi-z state). 9. drift data is based on a 1000 hour stress test at 125c. ac electrical characteristics: nv memory (-55c to +100c; v pu =3.0v to 5.5v) parameter symb ol condition min typ max units nv write cycle time t wr 21 0m s eeprom writes n eewr -55c to +55c 50k writes eeprom data retention t eedr -55c to +55c 10 years downloaded from: http:///
ds18s20-par 19 of 20 ac electrical characteristics (-55c to +100c; v pu =3.0v to 5.5v) parameter symbol condition min typ max units notes temperature conversion time t conv 750 ms 1 time to strong pullup on t spon start convert t or copy scratchpad command issued 10 s time slot t slot 60 120 s 1 recovery time t rec 1 s 1 write 0 low time r low0 60 120 s 1 write 1 low time t low1 11 5 s 1 read data valid t rdv 15 s 1 reset time high t rsth 480 s 1 reset time low t rstl 480 960 s 1,2 presence detect high t pdhigh 15 60 s 1 presence detect low t pdlow 60 240 s 1 capacitance c in/out 25 pf notes: 1. refer to timing diagrams in figure 16. 2. if t rstl > 960 s, a power on reset may occur. typical performance curve figure 15 ds18s20-par typical error curve -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 1 02 03 04 05 06 07 0 reference temp (c) thermometer error (c) mean error +3s error -3s error downloaded from: http:///
ds18s20-par 20 of 20 timing diagrams figure 16 downloaded from: http:///

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